Physical Interfaces

The AVR ONE! supports several hardware interfaces as described in the sections that follow.

JTAG

The JTAG interface consists of a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE 1149.1 standard. The IEEE standard was developed to provide an industry-standard way to efficiently test circuit board connectivity (Boundary Scan). Atmel® AVR devices have extended this functionality to include full Programming and On-Chip Debugging support.

Figure 3.1. JTAG interface basics

JTAG interface basics

When designing an application PCB which includes an AVR with the JTAG interface, it is recommended to use the pinout as shown in Figure 3.2, “JTAG header pinout”. The AVR ONE! ships with both 100-mil and 50-mil adapters supporting this pinout.

Figure 3.2. JTAG header pinout

JTAG header pinout

Table 3.1. JTAG pin description

NamePinDescription
TCK1Test Clock (clock signal from the AVR ONE! into the target device)
TMS5Teset Mode Select (control signal from the AVR ONE! into the target device)
TDI9Test Data In (data transmitted from the AVR ONE into the target device)
TDO3Test Data Out (data transmitted from the target device into the AVR ONE!)
nTRST8Test Reset (optional, only on some AVR devices). Used to reset the JTAG TAP controller
nSRST6Source Reset (optional) Used to reset the target device. Connecting this pin is recommended since it allows the AVR ONE! to hold the target device in a reset state, which can be essential to debugging in certain scenarios.
VTref4Target voltage reference. The AVR ONE! samples the target voltage on this pin in order to power the level converters correctly. The AVR ONE! draws less than 1mA from this pin.
GND2, 10Ground. Both must be connected to ensure that the AVR ONE! and the target device share the same ground reference.


Tip: remember to include a decoupling capacitor between pins 4 and 2.

The JTAG interface allows for several devices to be connected to a single interface in a daisy-chain configuration. The target devices must all be powered by the same supply voltage, share a common ground node, and must be connected as shown in Figure 3.3, “JTAG daisy-chain”.

Figure 3.3. JTAG daisy-chain

JTAG daisy-chain

The JTAG interface can be used as both a programming and debugging interface.

Auxiliary (AUX) Physical (including JTAG)

When debugging AVR target devices that feature an auxiliary port, it is recommended to use the 38-pin connector, which provides access to both JTAG and AUX ports. The AUX port facilitates advanced debugging features such as program trace.

The pinout of the 38-pin connector is shown in Figure 3.4, “Mictor Connector Pinout” and listed in Table 3.2, “Mictor Connector Pinout”.

The MICTOR Connector is available from Tyco Electronics (part number 2-5767004-2)

Figure 3.4. Mictor Connector Pinout

Mictor Connector Pinout

Table 3.2. Mictor Connector Pinout

NamePinDescription
TCK15Test Clock
TMS17Test Mode Select
TDI19Test Data In
TDO11Test Data Out
nTRST21Test Reset
nRESET9Source Reset
EVTI10Event In
EVTO32Event Out
MCKO34Message Clock Out
MSEO038Message Start/End Out [0]
MSEO136Message Start/End Out [1]
MDO030Message Data Out [0]
MDO128Message Data Out [1]
MDO226Message Data Out [2]
MDO324Message Data Out [3]
MDO422Message Data Out [4]
MDO520Message Data Out [5]
VREF12Target Voltage Reference
GND39-43Ground